• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The invention relates to a method of designing 3D circuits implemented by a processing device involving partitioning a 2D circuit representation in two or more levels, the 2D circuit representation defining circuit elements interconnected by d interconnected each based on at least one of its length, propagation delay and priority level, the 2D circuit representation initially forming a first level, the partitioning involving: a) selecting a first wire, interconnecting at least first and second circuit elements in the first level, which has a weight greater than a first threshold (WTH1); b) moving one of the first and second circuit elements connected by the selected wire to another level of the 3D circuit representation and replacing the interconnect wire with a connection via between the first and the other level; and c) repeat a) and b) for one or more other first level interconnecting wires.
    公开号:FR3028637A1
    申请号:FR1460962
    申请日:2014-11-13
    公开日:2016-05-20
    发明作者:Hossam Sarhan；Olivier Billoint；Fabien Clermidy；Sebastien Thuries
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD This invention relates to the field of integrated circuit design, and in particular to the design of three-dimensional circuits.
    [0002] DISCUSSION OF THE PRIOR ART In order to obtain better compactness and better performances, it has already been proposed to implement integrated circuits by using the so-called 3D technology in which two or more levels are stacked, each level comprising a semi-integrated layer. -conductor forming a 2D circuit, and the levels being interconnected by vias connection. Examples of 3D technologies include high-density silicon vias (HD-TSV) 3D technology, copper-on-copper technology, and monolithic 3D (M3D) integration technologies. The conEence 3D circuit design in general by a 2D circuit representation of the overall circuit, and involves a partitioning operation in which the various portions of the 2D circuit representation are assigned to the levels of the 3D circuit. The current partitioning methods that have been proposed use cost functions either to minimize the number of 3D vias in the 3D circuit representation, or to achieve a desired surface distribution between the levels. For example, the publication by J.Tada et al., Entitled "A Middle-Grain Circuit Partitioning Strategy for 3-D Integrated Floating-Point Multipliers", 3DIC, pages 1-6, IEEE 2011, describes such a partitioning method. which equalizes the surface of each layer and avoids as much as possible that the critical path passes through different layers. However, partitioning is a complex task, and 3D circuit designs made on the basis of existing partitioning methods tend to result in 3D circuits that are far from optimal in terms of performance and / or performance. of energy consumption. There is therefore a need in the art for a new method and device for partitioning a 2D circuit representation to generate a 3D circuit representation of a 3D circuit having performance and / or power consumption. relatively good. SUMMARY Thus, an embodiment of the present disclosure is to at least partially solve one or more problems of the prior art. In one aspect, there is provided a 3D circuit design method implemented by a processing device, the method comprising: partitioning a 2D circuit representation into two or more levels of a 3D circuit representation, the circuit representation 2D defining a plurality of circuit elements and a plurality of interconnect wires, each interconnect wire representing an electrical connection between two or more circuit elements, each interconnect wire being weighted on the basis of at least one one of: its length; its propagation delay; and its priority level based on the extent to which it represents a critical transmission path, the 2D circuit representation initially forming a first level of the 3D circuit representation, the partitioning comprising: 5 a ) selecting a first wire, interconnecting at least first and second circuit elements in the first level, which has a weight greater than a first threshold; b) moving one of the first and second circuit elements connected by the selected wire to another level of the 3D circuit representation and replacing the interconnect wire with a connection via the first level and the other level ; and c) repeat a) and b) for one or more other first level interconnecting wires. According to one embodiment, a) and b) are repeated until one or more of the following conditions have been satisfied: there are no longer interconnecting wires in the first level having a weight greater than first threshold; the login vias account has reached or exceeded a limit; a certain surface ratio between the first level and one or more other levels has been reached; and a certain power ratio between the first level and one or more other levels has been reached. According to one embodiment, the selection of a first wire comprises a ranking of the interconnect wires based on their weights, and the selection of the interconnect wire having the highest weight. According to one embodiment, the interconnection wires are weighted on the basis of their lengths, and the first threshold 30 is a length threshold. According to one embodiment, the length of the wires is estimated using a half-perimeter wire length model (HPWL). According to one embodiment, the method further comprises: d) identifying in the representation of the 3D circuit an interconnecting wire having a weight less than a second threshold and which has been replaced by a connection via ; e) restoring the identified interconnect wire by replacing the connecting via with an interconnecting wire between circuit elements in the same level; and f) repeating d) and e) until there is no longer any connection vias replacing interconnect wires which have a weight less than the second threshold. According to one embodiment, each circuit element in the 2D circuit representation comprises an indication of at least one of: its surface; and its energy consumption; the method further comprising: verifying whether a limit of a surface ratio limit, a power consumption ratio limit, and a connection vias count limit has been exceeded in the 3D circuit representation, and if so, restore one or more interconnect wires by replacing the connection via an interconnecting wire between circuit elements in the same level. According to one embodiment, the 2D circuit representation is a 2D interconnection list, and the partitioning of the 2D circuit representation comprises converting the 2D interconnect list into a hypergraph having vertices corresponding to the circuit elements. of the 2D circuit representation, and edges corresponding to the interconnect wires of the 2D circuit representation. According to one embodiment, the circuit elements are standard cells selected in a standard cell library.
    [0003] According to one embodiment, the circuit elements are semiconductor devices, at least one of the circuit elements being a transistor. According to one embodiment, the method further comprises: performing a routing placement on the 3D circuit representation to generate a 3D circuit design.
    [0004] According to one embodiment, the method further comprises fabricating an integrated circuit based on the 3D circuit design. In another aspect, there is provided a non-transient storage device storing a computer program which, when executed by carrying out the method According to another calculation comprising: a processing device, brings the aforesaid. In aspect, there is provided a device of one or more memories storing instructions and a 2D circuit representation; and a processing device adapted to generate, under the control of the instructions, a 3D circuit representation by: partitioning the 2D circuit representation into two or more levels of the 3D circuit representation, the 2D circuit representation defining a plurality of circuit elements and a plurality of interconnecting wires, each interconnecting wire representing an electrical connection between two or more circuit elements, each interconnect wire being weighted on the basis of at least one of: its length ; its propagation delay; and its priority level based on the extent in which it represents a critical transmission path, the 2D circuit representation initially forming a first level of the 3D circuit representation, the partitioning comprising: a) selecting a first wire interconnecting at least first and second circuit elements in the first level, which has a weight greater than a first threshold; b) moving one of the first and second circuit elements connected by the selected wire to another level of the 3D circuit representation and replacing the interconnect wire with a connection via the first level and the other level ; and c) repeat a) and b) for one or more other first level interconnecting wires.
    [0005] According to one embodiment, the first wire further interconnects one or more other circuit elements to the first and second circuit elements, and b) further comprises moving one or more of the other circuit elements. 5 to the other level. BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other features and advantages will be apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: Figure 1 is a sectional view of a portion of a 3D circuit comprising two levels according to an embodiment of the present description; Fig. 2 is a flowchart showing operations in a 3D circuit design method according to an exemplary embodiment of the present disclosure; FIGS. 3A to 3C are hypergraph representations of a circuit according to an exemplary embodiment of the present description; Fig. 4 is a flow chart showing in more detail operations in a 3D circuit design method according to an exemplary embodiment of the present disclosure; and FIG. 5 illustrates a computing device for generating a 3D circuit representation according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION In the following description, certain embodiments will be described based on the design of a 3D circuit that uses monolithic 3D technology. Such a technology is described in more detail in the P. Batude et al. Publication, entitled "Demonstration of low-temperature 3D sequential FDSOI integration down to 50 nm gate level", VLSI 3028637 B13593EN - DD15524 7 Technology (VLSIT), symposium on, IEEE, 2011, whose content is considered to be included here within the limits allowed by law. Such technology allows for example 3D via having diameters as small as 0.1 to 0.25 gm, a pitch as low as 0.2 to 0.5 gm, and a density of up to 25 million per mm 2. However, it will be apparent to those skilled in the art that the embodiments described herein could be applied to other 3D technologies, such as: copper-to-copper technology, which is for example described in more detail in the publication R. Taibi, et al., entitled "Full Characterization of Cu / Cu Direct Bonding for 3D Integration," Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th. IEEE, 2010, the content of which is considered to be included here within the limits permitted by law; and high density 3D via silicon vias (HD-TSV), which is for example described in more detail in the publication by H. Chaabouni, et al., entitled "Investigation on TSV impact on 65 "CMOS Devices and Circuits", Electron Devices Meeting (IEDM), IEEE International, 2010, the contents of which are considered to be included herein to the extent permitted by law. FIG. 1 is a sectional view of a portion 100 of a monolithic 3D integrated circuit according to an exemplary embodiment in which there are two levels, a lower level 102 and a higher level 104. While a 2D integrated circuit comprises in general a single semiconductor layer in which transistors are formed in substantially the same plane, in a 3D integrated circuit, each level comprises a semiconductor layer 106. The semiconductor layers 106 are for example silicon, and each The level also includes, for example, a metal layer 108, connecting devices in the semiconductor layer 106. CMOS (complementary MOS) devices 110 are distributed in the semiconductor layer 106, and correspond, for example, to standard cells consisting of Transistors 112. As is known to those skilled in the art, a standard cell is a group of transistors and interconnects which allows to perform a specific Boolean function or memory function. During circuit synthesis, a standard cell library is typically used in which each standard cell is represented by data describing its characteristics. For example, the features may include the Boolean function of the standard cell, represented for example by a truth table or the like, and the physical design of the standard cell, represented for example by a list of connections of the transistors and / or other devices which implement the standard cell, and / or by a plot. The metal layers 108 comprise metal interconnections 114, for example made of copper or other conductive material. Some of the interconnects connect transistors in a standard cell, while others form interconnect wires between standard cells. In addition, two connection vias 116, also referred to here as 3D vias, are shown in FIG. 1 and provide interconnections between the standard cells 110 in different levels. As mentioned previously, 3D vias 116 have for example diameters in the range of 0.1 to 0.25 gm in the case of monolithic 3D technology. In the case of HD-TSV technology or copper-on-copper technology, the via 3D 116 have for example diameters of about 3 gm.
    [0006] Compared to a 2D circuit, one advantage of a 3D circuit is that the surface can be reduced. In addition, as will be described in more detail below, it is possible to improve performance by significantly reducing the lengths of wires in the circuit. During the design of a 3D circuit, such as that of FIG. 2, the circuit is for example first generated in the form of a list of 2D interconnections defining the various standard cells which must form the circuit in a set. 2D implementation. The 2D interconnection list is then for example partitioned to define the standard cells that must form each level of the 3D circuit. FIG. 2 is a flowchart showing operations in a 3D circuit design method, and particularly in a method for generating a 3D circuit representation by partitioning a 2D level interconnection list in a circuit 3D. The method is for example implemented by software, in other words by a processing device under the control of instructions in an instruction memory. For example, the 2D interconnect list has been converted to a hypergraph representation. As will be described in more detail below, a hypergraph representation is comprised of vertex nodes that represent circuit elements, and hyper-edges that represent interconnection wires between the circuit elements. The term "circuit element" is used herein to refer to any granularity of devices in the circuit, which could correspond to individual semiconductor devices, such as transistors, capacitors, or resistors, or to groups of semiconductor devices. conductors, such as logic gates or larger devices, for example implemented by standard cells. In the case of capacitors and resistors, they are for example defined by a synthesized interconnection list, in other words a list of interconnections generated by a synthesis process on the basis of standard cell libraries. In the case of transistors, a more detailed interconnection list, such as a SPICE interconnection list, is for example used to define the transistors and to estimate the interconnections of cabling between the transistors. The hypergraph representation allows for example to apply a weighting to vertex nodes, and also to hyper-edges. It will be assumed here that at least the hyper-edges have been weighted. The weight is for example based on the potential performance gain that could be obtained if the wire is replaced by a 3D via, and the higher the potential performance gain, the higher the weighting. The main performance characteristic of a wire is its length, since the longer the wire is, the greater its RC value, and therefore the greater the delay and power consumption of the wire. Each weight is therefore generated for example on the basis of the length of the corresponding interconnection wire and / or the propagation delay of the corresponding interconnection wire. Instead, or in addition, the wires could be weighted on the basis of their priority level in view of the signals they propagate, the weight indicating for example the degree to which the wire represents a critical transmission path in the design. of 2D circuit. Priority levels are, for example, assigned to critical design paths, such as, for example, the clock signal, the reset signal and / or the control signals. These signals are specific to each design. It will be apparent to those skilled in the art that, rather than a hypergraph representation, other representations of the 2D circuit could be used to apply weighting to the connection wires. It will be assumed that the number of levels in the 3D circuit representation has been chosen by a user or otherwise determined. In addition, although some circuit elements may be set at particular levels prior to partitioning, it will be assumed that all non-circuit circuit elements in the 2D interconnection list are initially assigned to a first level of the 3D circuit representation. . In a first operation 201, a first wire of the 2D interconnection list, interconnecting at least first and second circuit elements in the first level, and having a weight greater than a first threshold WTH1, is selected. In some embodiments, the wire may further interconnect the first and second circuit elements to one or more other circuit elements. This selection is, for example, made by classifying the interconnecting wires in an order based on their weight, and initially selecting the highest rank interconnecting wire, i.e. yarn with the highest weight. As will be described in more detail below, the threshold WTH1 is for example chosen on the basis of the performance of a 3D via the given technology with respect to an interconnecting wire having a given weighting. In a second operation 202, one of the first and second circuit elements is moved to another level of the 3D circuit design, and the selected interconnect wire is replaced by a 3D via. The choice between moving the first or the second circuit element to the other level is for example based on the weighting of the other interconnection wires of each circuit element, and / or on other physical characteristics of the first and second circuits. circuit elements, such as surface area or energy consumption. In addition, in the case where the selected interconnection wire interconnects more than two circuit elements, more than one of the circuit elements can be moved to the other level. In one embodiment, up to half the number of circuit elements interconnected by the selected wire is moved to the other level. The selected interconnect wire is cut, in other words it is designated as being replaced by a 3D via between the first level and the other level. In addition, all other interconnecting wires connecting the shifted circuit element to other circuit elements in the first level will also be cut, and replaced by 3D vias. In a third operation 203, it is determined whether there are other interconnection wires in the first level which have a weight greater than the threshold WTH1- If yes, the operations 201 and 202 are repeated for a new wire. interconnection in the first level. These operations are repeated, for example, until there are no more wires in the first level having a weighting higher than the threshold WTH1. When this is the case, the following operation after the operation 203 goes In some embodiments, operation 203 may also include a check of one or more other criteria, such as a limit in the area ratio or the ratio. of power between levels or a limit in the number of 5 3D vias, and the method may proceed to operation 204 if one or more of these other criteria is satisfied. In operation 204, the process can be terminated. As a variant, one or more of the cut-off interconnection wires may be restored if their weight was less than another WTH2 threshold, their cut leading for example to a significant performance degradation. Alternatively or additionally, one or more cut-off interconnect wires may be restored if the overall number of allowed 3D vias or the 3D vias density limit has been exceeded, or if a target region or power distribution between them is exceeded. levels have not been reached. FIG. 3A illustrates an example of hypergraph 300 in which there are five vertex nodes representing circuit elements referenced 1 to 5. These vertex nodes are for example assigned weights of 100, 75, 270, 320 and 140 respectively, which In this example represent their respective surfaces. In addition, hyper-edges are shown connecting the vertex nodes and representing interconnections between the circuit elements. The hyper-edges are weighted, the weights going from 3 to 12 in this example, this weight representing for example the length of the corresponding thread. FIG. 3B illustrates the same hypergraph 300 as in FIG. 3A, and also illustrates, by a dotted line 302, a possible partitioning of the circuit elements, in two levels if the main criterion is the equalization of the surface in each one. levels. Indeed, the circuit elements 1, 2, 3 are grouped, resulting in a total surface weight of 445, which is close to the total surface weight of 460 of the remaining circuit elements 4 and 5. However, yarns having weights of 3 and 4 are cut in accordance with this partitioning strategy, and those having weights of 10 and 12 have not been cut, which implies relatively poor performance. of the 3D circuit resulting from this design in terms of time and energy consumption. FIG. 3C also illustrates the same hypergraph 300 as in FIG. 3A, and illustrates, by a dashed line 304, a partitioning of the circuit elements. in two levels in accordance with the partitioning method described herein on the basis of the weights of the interconnect wires. Thus, the weighted yarns 10 and 12 are cut, as well as the weighted yarns 6 and 7, and the weighted yarns 3, 4 and 5 remain intact, which implies better performance of the 3D circuit resulting from this design in terms of delay. and energy consolimation, compared with the case of Figure 3B. Fig. 4 is a flowchart illustrating operations in a 3D circuit design method according to an exemplary embodiment. In a first operation 401, the list of 2D interconnects is generated, for example by a circuit designer using a standard cell library.
    [0007] In a subsequent operation 402, the 2D interconnection list is partitioned. This implies, for example, sub-operations 403 to 416, as will be described now. In operation 403, the 2D interconnect list is converted into a hypergraph representation, appropriate representation. In an operation OR another following 404, the hypergraph is weighted with weights to be used during the partitioning algorithm. For example, at least each hyper-edge of the hypergraph is weighted with a numerical value representing its weight. As has been described above, the weights are for example based on the physical characteristics of the corresponding wires. In the case where each wire is weighted on the basis of the length of the wire, the lengths of wire can be determined by performing a routing operation on the 2D interconnection list. Alternatively, a half-perimeter (HPWL) wire length model could be used to estimate wire lengths, according to which the wire length of each interconnection is for example calculated on the basis of the length of wire. addition of the width and height of the standard cells that it connects. The width and the height of the standard cells are for example defined in the standard cell library. Additionally, each vertex may be weighted based on physical characteristics of the corresponding circuit element, such as its physical cell area, leakage current, or internal power consumption. In a subsequent operation 405, partitioning of the hypergraph is performed. These operations involve sub-operations 406 to 415. In the operation 406, for example, a list of "fixed cells" is generated, listing the cells that must be placed in certain levels of the 3D circuit, and giving an indication of the level. in which they must be placed. This list is for example defined by the user, and can be generated automatically on the basis of a user specification file. For example, all ports in the design could be located in one of the levels, and so it might be desirable for all circuit elements connected to ports to be located in that level. In addition to or instead, the circuit design may include a synchronous clock tree in one of the levels, and thus all standard clock-driven cells may be set in this level and are part of the cell list. fixed. In a subsequent operation 407, the multi-threshold partitioning algorithm described above and based on weight thresholds WTH1 and WTH2 is implemented. This operation involves sub-operations 408 to 414. In operation 408, the interconnecting wires are, for example, ranked in descending order on the basis of their respective weights. For example, the interconnecting wires are arranged from the longest to the shortest.
    [0008] In a following operation 409, the fixed cells indicated by the list generated in the operation 406 are for example marked. For example, cells in the "fixed cell" list generated in operation 406 are identified so that these cells do not transfer from one level to another during subsequent partitioning operations. . In a subsequent operation 410, the interconnect wires having weights greater than the threshold WTH1 are cut off, and replaced by vias, as previously described. This operation is for example iterative, the list of connections being re-evaluated after each cut, and for example can stop when there are no more threads having weightings higher than WTH1, or when another criterion, such as a ratio of surface area AR, was satisfied. In a following operation 411, all interconnect wire cuts having a weighting lower than the threshold WTH2 are for example restored. The threshold WTH2 is different from the threshold WTH1, for example lower. For example, a weight value WU may be set to correspond to an interconnect wire having a performance equivalent to a via 3D. The threshold WTH1 is, for example, chosen to be greater than Wv, and the threshold WTH2 is for example chosen to be equal to or less than W. In a following operation 412, the 3D vias account 25 is optionally fixed, if a limit in the number or the density via 3D has been passed. This is for example obtained by restoring one or more interconnecting wires, starting with those having the lowest weight. For example, the yarns are ranked in the order of lowest weight to highest weight, and the yarns are restored starting from the lowest weight until the number of 3D vias or the limit density are no longer exceeded. In a subsequent operation 413, the surface ratio between the levels in the 3D design is optionally set if a desired surface ratio has not been achieved. For example, it may be desired that the surface ratio in the case of a two-level design falls between limits a and b, where a is for example 40/60, and b is 60/40. in other words, a given level is not less than 40% nor more than 60% of the total area. If the desired area ratio has not been achieved, one or more of the interconnecting wires can be restored, again starting with the ones with the lowest weight. Alternatively, in order to reduce the number of interconnect wires that are restored, the wires that are associated with the circuit elements having the highest surface could be restored first. Although not shown in FIG. 4, rather than, or in addition to, setting a surface ratio between levels, a power ratio can also be similarly set, assuming that the power consumed by each circuit is known. In a subsequent operation 414, the final partition in levels of the 3D circuit is for example generated, accompanied by its ratio or surface ratios between the levels, and the 3D vias count. After the multi-threshold partitioning algorithm 407, the next operation is the operation 415, in which the partitioned hypergraph files are generated, thus completing the multi-threshold partitioning method.
    [0009] After the hypergraph partitioning operation 405, the following operation is the operation 416, in which the hypergraph is, for example, converted back to a list of interconnections, the interconnection list being a partitioned interconnection list. 3D defining the 2D circuit associated with each level 30 of the 3D design. For example, the 3D interconnection list distinguishes between interconnect wires in the same level and 3D vias between levels. For example, the 3D interconnection list includes a list of 2D interconnections for each level, and a list of interconnections of a higher hierarchical level defining the connections between the lists of interconnections. 2D interconnections, each of these connections representing a 3D via. After partitioning the 2D interconnect list to generate the 3D partitioned interconnection list by operations 402, a subsequent operation 417 for example involves performing a routing placement based on the 3D partitioned interconnection list. . Routing placement involves, for example, a first step of deciding where to place each circuit element in its respective level, and a second stage of designing interconnect wires and 3D vias to interconnect the elements of the circuit. For example, as previously mentioned, the 3D interconnection list may include a list of 2D interconnections for each level, and a hierarchical list of superior level interconnections, and this step involves performing a routing placement on each list of interconnections 2D, the interconnections between the lists of interconnections 2D indicated by the list of interconnections of higher level being implemented in the form of vias.
    [0010] In a following operation 418, one or more 3D circuits are for example fabricated on the basis of the 3D circuit design generated by the routing placement operation 417. FIG. 5 schematically illustrates a computing device 500 for implementing the partitioning method of FIG. 2 and / or operation 402 of FIG. 4 as previously described. The computing device 500 comprises, for example, a processing device 502, which may comprise one or more processors under the control of instructions stored by an instruction memory 504. A memory 506, which may be integrated with the memory 504 or A separate memory device is also coupled to the processing device 502, and for example stores the 2D interconnection list before partitioning, and the 3D partitioned interconnection list 3028637 B13593EN - DD15524 18 after the implementation of the partitioning by the processing device 502. A communication interface 508 is also for example designed to couple the processing device 502 to one or more networks and, for example, to allow the transmission of the 3D circuit design to a factory for manufacturing. One or more input devices 510 and a display 512 may also provide a user interface allowing a user to enter certain parameters during the partitioning process, for example to define the number of levels of the 3D circuit, and / or or to indicate the circuit elements that must be set at a given level. One advantage of the 3D partitioning methods described herein, based on weighted interconnect wires, is that it leads to 3D circuits having better performance than circuits generated using other partitioning methods. With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example, although the case of a two-level 3D circuit design has been described here, the manner in which this method could be extended more generally to 3D circuits having N levels, where N is an integer greater than or equal to at 2, will be clear to those skilled in the art. For example, in one embodiment, the algorithm described herein in connection with Fig. 2 is applied at a first level using a relatively high wire length threshold to transfer about 1 / N of the 2D circuit to a second level. adjacent, for example on the basis of the surface or energy consumption criterion of each circuit element. The algorithm is then re-applied to the first level, for example, using a lower wire length threshold to transfer about another 1 / N proportion of the initial 2D circuit to a third adjacent level, again based on of the surface area or energy consumption criterion. This process is repeated, for example, until about 1 / N of the circuit remains in the first level. In addition, whenever the algorithm is applied at two levels, the thread length threshold is, for example, adjusted on the basis of the distance separating the two levels. Indeed, this distance will determine the length of the 3D vias, and thus their technology parameters, like their parasitic effects. Furthermore, although a method has been described in which selected interconnect wires are cut, and some wires are restored if they are shorter in length than another WTH2 length threshold, alternative algorithms would be possible. For example, it will be possible to group the interconnected circuit elements by wires shorter than the other length threshold WTH2, and to treat each group of circuit elements as a single circuit element when applying the circuit. partitioning process described here. However, an advantage of allowing short interconnections to be cut and then restored is that, by this process, the two circuit elements connected by the short interconnection can be moved to another level, rather than remaining in the initial level, which leads to a better balanced partitioning. In addition, although embodiments based on MOS transistor technology have been described, it will be apparent to those skilled in the art that the techniques described herein could be applied to other technologies.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. A method of designing a 3D circuit implemented by a processing device, the method comprising: partitioning a 2D circuit representation into two or more levels of a 3D circuit representation, the 2D circuit representation defining a plurality of elements circuit board and a plurality of interconnect wires, each interconnect wire representing an electrical connection between two or more circuit elements, each interconnect wire being weighted based on at least one of: its length; its propagation delay; and its priority level based on the extent in which it represents a critical transmission path, the 2D circuit representation initially forming a first level of the 3D circuit representation, the partitioning comprising: a) selecting a first wire interconnecting at least first and second circuit elements in the first level, which has a weight greater than a first threshold (WTH1); b) moving one of the first and second circuit elements connected by the selected wire to another level of the 3D circuit representation and replacing the interconnect wire with a connecting via between the first level and the other level ; and c) repeat a) and b) for one or more other first level interconnecting wires. 25
    [0002]
    The method according to claim 1, wherein a) and b) are repeated until one or more of the following conditions have been satisfied there are no longer interconnecting wires in the first level having a higher weight. at the first threshold; The connection vias count has reached or exceeded a limit; a certain surface ratio between the first level and one or more other levels has been reached; and a certain power ratio between the first level and one or more other levels has been reached.
    [0003]
    The method of claim 1 or 2, wherein selecting a first wire comprises ranking the interconnect wires based on their weights, and selecting the interconnect wire having the highest weight.
    [0004]
    The method of any one of claims 1 to 3, wherein the interconnect wires are weighted based on their lengths, and wherein the first threshold is a length threshold.
    [0005]
    The method of claim 4, wherein the length of the wires is estimated using a half-perimeter wire length (HPWL) model.
    [0006]
    The method of any one of claims 1 to 5, further comprising: d) identifying in the representation of the 3D circuit an interconnect wire having a weight less than a second threshold (WTH2) and which has been replaced by a connection via: e) restoring the identified interconnecting wire by replacing the connecting via with an interconnecting wire between circuit elements in the same level; and f) repeating d) and e) until there are no more connecting vias replacing interconnect wires which have a weight less than the second threshold (WTH2) - 25
    [0007]
    The method of any one of claims 1 to 6, wherein each circuit element in the 2D circuit representation comprises an indication of at least one element across its surface; and its energy consumption; the method further comprising: checking whether a limit of a surface ratio limit, a power consumption ratio limit and a connection vias count limit has been exceeded in the 3D circuit representation, and whether yes, restore one or more interconnect wires by replacing the connecting via with an interconnecting wire between circuit elements in the same level.
    [0008]
    The method of any one of claims 1 to 7, wherein the 2D circuit representation is a 2D interconnect list, and the partitioning of the 2D circuit representation comprises converting the 2D interconnect list into a 2D interconnect list. hypergraph having vertices corresponding to the circuit elements of the 2D circuit representation, and edges corresponding to the interconnect wires of the 2D circuit representation.
    [0009]
    The method of any one of claims 1 to 8, wherein the circuit elements are standard cells selected from a standard cell library.
    [0010]
    The method of any one of claims 1 to 8, wherein the circuit elements are semiconductor devices, wherein at least one of the circuit elements is a transistor.
    [0011]
    The method of any one of claims 1 to 10, further comprising placing and routing on the 3D circuit representation to generate a 3D circuit design.
    [0012]
    A method comprising manufacturing an integrated circuit based on the 3D circuit design generated by the method of claim 11.
    [0013]
    13. Non-transient storage device storing a computer program which, when executed by a processing device, brings about the implementation of the method of any one of claims 1 to 11.
    [0014]
    A computing device comprising: one or more memories (504, 506) storing instructions and a 2D circuit representation; and a processing device (502) adapted to generate, under the control of the instructions, a 3D circuit representation By partitioning the 2D circuit representation into two or more levels of the 3D circuit representation, the 2D circuit representation defining a plurality of circuit elements and a plurality of interconnect wires, each interconnect wire. representing an electrical connection between two or more circuit elements, each interconnect wire being weighted on the basis of at least one of: its length; its propagation delay; and its priority level on the basis of the extent in which it represents a critical transmission path, the 2D circuit representation initially forming a first level of the 3D circuit representation, the partitioning comprising: a) selecting a first thread interconnecting at least first and second circuit elements in the first level, which has a weight greater than a first threshold (wmi) b) moving one of the first and second circuit elements connected by the selected wire to another level of the 3D circuit representation and replace the interconnect wire with a connection via the first level and the other level; and c) repeat a) and b) for one or more other first level interconnecting wires.
    [0015]
    The computing device of claim 14, wherein the first wire further interconnects one or more other circuit elements to the first and second circuit elements, and further comprises moving one or more of the other elements. circuit to the other level.
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    同族专利:
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    EP3021242A1|2016-05-18|
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    法律状态:
    2015-11-25| PLFP| Fee payment|Year of fee payment: 2 |
    2016-05-20| PLSC| Search report ready|Effective date: 20160520 |
    2016-11-30| PLFP| Fee payment|Year of fee payment: 3 |
    2017-11-30| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1460962|2014-11-13|
    FR1460962A|FR3028637B1|2014-11-13|2014-11-13|METHOD FOR DESIGNING 3D CIRCUITS|FR1460962A| FR3028637B1|2014-11-13|2014-11-13|METHOD FOR DESIGNING 3D CIRCUITS|
    EP15194328.9A| EP3021242A1|2014-11-13|2015-11-12|3d circuit design method|
    US14/941,331| US9922151B2|2014-11-13|2015-11-13|3D circuit design method|
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